High data rate decoding of forward error correction-encoded digital information signals is limited primarily by the signal processing speed of available decoder hardware. In particular, in an airborne/spacecraft environment, wherein payload and occupancy constraints limit the size of the signal processing resources that may be installed in the vehicle, the freedom to simply add another circuit board of signal processing components in order to obtain the requisite signal processing capacity/speed is effectively non-existent. Consequently, the system designer is often forced to employ an error correction encoding mechanism (such as block coding approach), the execution of which is less hardware intensive than a higher performance scheme and which, unfortunately, suffers when compared to a (preferred) convolutional coding technique.
One proposal to increase the speed of high performance/high speed signal processors used for high data rate encoding and decoding of convolutional code-based forward error correction schemes has been to separate or divide the encoder (at the transmitter site) and the decoder (at the receiver site) into respective pluralities of lower data rate signal processors that operate, in parallel, on subdivided portions of the data stream. Namely, at the transmitter site, the data stream is separated (demultiplexed) into a plurality of individual portions that are separately encoded by the lower data rate encoders and then recombined for transmission over the communication channel. At the receiver site, the encoded data stream is once again separated into a plurality of signal paths containing low data rate decoders, which decode the respective segments of the encoded data stream. These decoded segments are then multiplexed into an output data stream that is intended to replicate the original information signals.
Because of the use of lower data rate encoder/decoding mechanisms, the sought-after error correction capabilities provided by convolutional codes can be employed. Unfortunately, however, this approach requires a substantial increase in hardware at the transmitter site (multiple encoders).